{"id":102209,"date":"2025-03-19T12:37:43","date_gmt":"2025-03-19T09:07:43","guid":{"rendered":"https:\/\/nabfollower.com\/blog\/%da%86%da%af%d9%88%d9%86%d9%87-%d8%a2%d8%af%d8%b1%d8%b3-ip-%d8%a7%d8%b2-%d8%b5%d9%81%d8%ad%d9%87-fpga-%d8%b1%d8%a7-%da%a9%d9%87-%d8%a7%d8%b2-%d8%b7%d8%b1%db%8c%d9%82-matlab-%d9%85%d8%aa%d8%b5%d9%84\/"},"modified":"2025-03-19T12:37:43","modified_gmt":"2025-03-19T09:07:43","slug":"%da%86%da%af%d9%88%d9%86%d9%87-%d8%a2%d8%af%d8%b1%d8%b3-ip-%d8%a7%d8%b2-%d8%b5%d9%81%d8%ad%d9%87-fpga-%d8%b1%d8%a7-%da%a9%d9%87-%d8%a7%d8%b2-%d8%b7%d8%b1%db%8c%d9%82-matlab-%d9%85%d8%aa%d8%b5%d9%84","status":"publish","type":"post","link":"https:\/\/nabfollower.com\/blog\/%da%86%da%af%d9%88%d9%86%d9%87-%d8%a2%d8%af%d8%b1%d8%b3-ip-%d8%a7%d8%b2-%d8%b5%d9%81%d8%ad%d9%87-fpga-%d8%b1%d8%a7-%da%a9%d9%87-%d8%a7%d8%b2-%d8%b7%d8%b1%db%8c%d9%82-matlab-%d9%85%d8%aa%d8%b5%d9%84\/","title":{"rendered":"\u0686\u06af\u0648\u0646\u0647 \u0622\u062f\u0631\u0633 IP \u0627\u0632 \u0635\u0641\u062d\u0647 FPGA \u0631\u0627 \u06a9\u0647 \u0627\u0632 \u0637\u0631\u06cc\u0642 MATLAB \u0645\u062a\u0635\u0644 \u0627\u0633\u062a \u067e\u06cc\u062f\u0627 \u06a9\u0646\u06cc\u0645\u061f"},"content":{"rendered":"<div data-article-id=\"2342606\" id=\"article-body\">\n<p>\u0628\u0631\u0627\u06cc \u06cc\u0627\u0641\u062a\u0646 \u0622\u062f\u0631\u0633 IP \u06cc\u06a9 \u0635\u0641\u062d\u0647 FPGA \u06a9\u0647 \u0627\u0632 \u0637\u0631\u06cc\u0642 MATLAB \u0645\u062a\u0635\u0644 \u0627\u0633\u062a \u060c \u0628\u0647 \u0637\u0648\u0631 \u0645\u0639\u0645\u0648\u0644 \u0628\u0627\u06cc\u062f \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u06cc\u06a9 \u0631\u0627\u0628\u0637 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc \u0634\u062f\u0647 (\u0628\u0647 \u0639\u0646\u0648\u0627\u0646 \u0645\u062b\u0627\u0644 \u060c \u0627\u062a\u0631\u0646\u062a \u060c JTAG \u06cc\u0627 PCIE) \u0627\u0631\u062a\u0628\u0627\u0637 \u0628\u06cc\u0646 MATLAB \u0648 \u0635\u0641\u062d\u0647 FPGA \u0628\u0631\u0642\u0631\u0627\u0631 \u06a9\u0646\u06cc\u062f. \u0645\u0631\u0627\u062d\u0644 \u062f\u0642\u06cc\u0642 \u0628\u0647 \u0635\u0641\u062d\u0647 FPGA \u060c \u067e\u0631\u0648\u062a\u06a9\u0644 \u0627\u0631\u062a\u0628\u0627\u0637\u06cc \u0648 \u0627\u0628\u0632\u0627\u0631\u06cc \u06a9\u0647 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0645\u06cc \u06a9\u0646\u06cc\u062f \u0628\u0633\u062a\u06af\u06cc \u062f\u0627\u0631\u062f. \u062f\u0631 \u0632\u06cc\u0631 \u06cc\u06a9 \u0631\u0627\u0647\u0646\u0645\u0627\u06cc \u06a9\u0644\u06cc \u0628\u0631\u0627\u06cc \u06cc\u0627\u0641\u062a\u0646 \u0622\u062f\u0631\u0633 IP \u06cc\u06a9 \u0635\u0641\u062d\u0647 FPGA \u0645\u062a\u0635\u0644 \u0628\u0647 MATLAB \u0648\u062c\u0648\u062f \u062f\u0627\u0631\u062f:<\/p>\n<p><img decoding=\"async\" src=\"https:\/\/media2.dev.to\/dynamic\/image\/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto\/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fedmf99x4ky2y3tdbtr2c.png\" alt=\"\u0634\u0631\u062d \u062a\u0635\u0648\u06cc\u0631\" loading=\"lazy\" width=\"777\" height=\"627\" title=\"\"><\/p>\n<p><strong>1. \u0627\u0637\u0645\u06cc\u0646\u0627\u0646 \u062d\u0627\u0635\u0644 \u06a9\u0646\u06cc\u062f \u06a9\u0647 \u0635\u0641\u062d\u0647 FPGA \u0645\u062a\u0635\u0644 \u0627\u0633\u062a<\/strong><\/p>\n<ul>\n<li>\u0635\u0641\u062d\u0647 FPGA \u0631\u0627 \u0627\u0632 \u0637\u0631\u06cc\u0642 \u0627\u062a\u0631\u0646\u062a \u060c JTAG \u06cc\u0627 \u06cc\u06a9 \u0631\u0627\u0628\u0637 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc \u062f\u06cc\u06af\u0631 \u0628\u0647 \u0631\u0627\u06cc\u0627\u0646\u0647 \u062e\u0648\u062f \u0648\u0635\u0644 \u06a9\u0646\u06cc\u062f.<\/li>\n<li>\u0642\u062f\u0631\u062a \u0631\u0648\u06cc \u0635\u0641\u062d\u0647 FPGA \u0648 \u0627\u0637\u0645\u06cc\u0646\u0627\u0646 \u062d\u0627\u0635\u0644 \u06a9\u0646\u06cc\u062f \u06a9\u0647 \u0628\u0647 \u062f\u0631\u0633\u062a\u06cc \u0628\u0631\u0627\u06cc \u0627\u0631\u062a\u0628\u0627\u0637\u0627\u062a \u0634\u0628\u06a9\u0647 (\u062f\u0631 \u0635\u0648\u0631\u062a \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0627\u062a\u0631\u0646\u062a) \u062a\u0646\u0638\u06cc\u0645 \u0634\u062f\u0647 \u0627\u0633\u062a.<\/li>\n<\/ul>\n<p><strong>\u062a\u0631\u062a\u06cc\u0628 \u0627\u0632 \u0628\u0633\u062a\u0647 \u0647\u0627\u06cc \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc Matlab \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f<\/strong><br \/>MATLAB \u0628\u0633\u062a\u0647 \u0647\u0627\u06cc \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc \u0631\u0627 \u0628\u0631\u0627\u06cc \u062a\u0627\u0628\u0644\u0648\u0647\u0627\u06cc FPGA \u0645\u0627\u0646\u0646\u062f Xilinx \u0648 Intel (AlterA) \u0641\u0631\u0627\u0647\u0645 \u0645\u06cc \u06a9\u0646\u062f. \u0627\u06cc\u0646 \u0628\u0633\u062a\u0647 \u0647\u0627 \u0627\u063a\u0644\u0628 \u0634\u0627\u0645\u0644 \u062a\u0648\u0627\u0628\u0639 \u062a\u0634\u062e\u06cc\u0635 \u0648 \u0628\u0631\u0642\u0631\u0627\u0631\u06cc \u0627\u0631\u062a\u0628\u0627\u0637 \u0628\u0627 \u0635\u0641\u062d\u0647 FPGA \u0647\u0633\u062a\u0646\u062f.<\/p>\n<p><strong>A. \u0628\u0633\u062a\u0647 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc FPGA \u0631\u0627 \u0646\u0635\u0628 \u06a9\u0646\u06cc\u062f<\/strong><\/p>\n<ul>\n<li>Matlab \u0631\u0627 \u0628\u0627\u0632 \u06a9\u0646\u06cc\u062f.<\/li>\n<li>\u0628\u0647 \u0645\u0646\u0648\u06cc \u0627\u0641\u0632\u0648\u062f\u0646\u06cc\u0647\u0627 \u0628\u0631\u0648\u06cc\u062f \u0648 \u0628\u0633\u062a\u0647 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc FPGA \u0631\u0627 \u0628\u0631\u0627\u06cc \u0635\u0641\u062d\u0647 \u062e\u0648\u062f \u062c\u0633\u062a\u062c\u0648 \u06a9\u0646\u06cc\u062f (\u0628\u0647 \u0639\u0646\u0648\u0627\u0646 \u0645\u062b\u0627\u0644 \u060c &#8220;\u0628\u0633\u062a\u0647 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc Xilinx FPGA&#8221; \u06cc\u0627 &#8220;\u0628\u0633\u062a\u0647 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc FPGA Intel&#8221;).<\/li>\n<li>\u0628\u0633\u062a\u0647 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc \u0631\u0627 \u0646\u0635\u0628 \u06a9\u0646\u06cc\u062f.<\/li>\n<\/ul>\n<p><strong>\u0628 &#8211; \u0635\u0641\u062d\u0647 FPGA \u0631\u0627 \u062a\u0634\u062e\u06cc\u0635 \u062f\u0647\u06cc\u062f<\/strong><br \/>\u0628\u0631\u0627\u06cc \u062a\u0634\u062e\u06cc\u0635 \u0635\u0641\u062d\u0647 FPGA \u0648 \u0622\u062f\u0631\u0633 IP \u0622\u0646 \u0627\u0632 \u062f\u0633\u062a\u0648\u0631\u0627\u062a MATLAB \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n<p>\u0645\u062b\u0627\u0644 \u0628\u0631\u0627\u06cc \u062a\u0627\u0628\u0644\u0648\u0647\u0627\u06cc Xilinx:<\/p>\n<div class=\"highlight js-code-highlight\">\n<pre class=\"highlight plaintext\"><code>matlab\n\n% List all FPGA boards connected to the host\nhw = xilinx.fpga.Board.listAvailableBoards();\n\n% Display the IP address of the first detected board\nif ~isempty(hw)\n    disp(hw(1).IPAddress);\nelse\n    disp('No FPGA board detected.');\nend\n<\/code><\/pre>\n<div class=\"highlight__panel js-actions-panel\">\n<div class=\"highlight__panel-action js-fullscreen-code-action\">\n    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-on\"><title>\u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u0631\u0627 \u0648\u0627\u0631\u062f \u06a9\u0646\u06cc\u062f<\/title>\n    <path d=\"M16 3h6v6h-2V5h-4V3zM2 3h6v2H4v4H2V3zm18 16v-4h2v6h-6v-2h4zM4 19h4v2H2v-6h2v4z\"\/>\n<\/svg><\/p>\n<p>    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-off\"><title>\u0627\u0632 \u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u062e\u0627\u0631\u062c \u0634\u0648\u06cc\u062f<\/title>\n    <path d=\"M18 7h4v2h-6V3h2v4zM8 9H2V7h4V3h2v6zm10 8v4h-2v-6h6v2h-4zM8 15v6H6v-4H2v-2h6z\"\/>\n<\/svg><\/p>\n<\/div>\n<\/div>\n<\/div>\n<p><strong>3 \u0628\u0631\u0627\u06cc \u06cc\u0627\u0641\u062a\u0646 \u0622\u062f\u0631\u0633 IP \u0627\u0632 \u062f\u0633\u062a\u0648\u0631\u0627\u062a \u0633\u06cc\u0633\u062a\u0645 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f<\/strong><br \/>\u0627\u06af\u0631 \u0647\u06cc\u0626\u062a \u0645\u062f\u06cc\u0631\u0647 FPGA \u0627\u0632 \u0637\u0631\u06cc\u0642 \u0627\u062a\u0631\u0646\u062a \u0628\u0647 \u0647\u0645 \u0648\u0635\u0644 \u0634\u0648\u062f \u060c \u0645\u06cc \u062a\u0648\u0627\u0646\u06cc\u062f \u0627\u0632 \u062f\u0633\u062a\u0648\u0631\u0627\u062a \u0633\u06cc\u0633\u062a\u0645 \u0628\u0631\u0627\u06cc \u06cc\u0627\u0641\u062a\u0646 \u0622\u062f\u0631\u0633 IP \u0622\u0646 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n<p><strong>A. \u0635\u0641\u062d\u0647 FPGA \u0631\u0627 \u067e\u06cc\u0646\u06af \u06a9\u0646\u06cc\u062f<\/strong><br \/>\u0628\u0631\u0627\u06cc \u0634\u0646\u0627\u0633\u0627\u06cc\u06cc \u0622\u062f\u0631\u0633 IP \u0647\u06cc\u0626\u062a \u0645\u062f\u06cc\u0631\u0647 FPGA \u0627\u0632 \u062f\u0633\u062a\u0648\u0631 \u067e\u06cc\u0646\u06af \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n<p>\u0645\u062b\u0627\u0644:<\/p>\n<div class=\"highlight js-code-highlight\">\n<pre class=\"highlight plaintext\"><code>matlab\n\n% Ping the FPGA board (replace 'fpga_hostname' with the board's hostname)\n[status, result] = system('ping fpga_hostname');\n\n% Display the result\ndisp(result);\n<\/code><\/pre>\n<div class=\"highlight__panel js-actions-panel\">\n<div class=\"highlight__panel-action js-fullscreen-code-action\">\n    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-on\"><title>\u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u0631\u0627 \u0648\u0627\u0631\u062f \u06a9\u0646\u06cc\u062f<\/title>\n    <path d=\"M16 3h6v6h-2V5h-4V3zM2 3h6v2H4v4H2V3zm18 16v-4h2v6h-6v-2h4zM4 19h4v2H2v-6h2v4z\"\/>\n<\/svg><\/p>\n<p>    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-off\"><title>\u0627\u0632 \u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u062e\u0627\u0631\u062c \u0634\u0648\u06cc\u062f<\/title>\n    <path d=\"M18 7h4v2h-6V3h2v4zM8 9H2V7h4V3h2v6zm10 8v4h-2v-6h6v2h-4zM8 15v6H6v-4H2v-2h6z\"\/>\n<\/svg><\/p>\n<\/div>\n<\/div>\n<\/div>\n<p><strong>\u0628 &#8211; \u0634\u0628\u06a9\u0647 \u0631\u0627 \u0627\u0633\u06a9\u0646 \u06a9\u0646\u06cc\u062f<\/strong><br \/>\u0627\u0632 \u0627\u0628\u0632\u0627\u0631\u0647\u0627\u06cc\u06cc \u0645\u0627\u0646\u0646\u062f ARP \u06cc\u0627 NMAP \u0628\u0631\u0627\u06cc \u0627\u0633\u06a9\u0646 \u0634\u0628\u06a9\u0647 \u0628\u0631\u0627\u06cc \u062f\u0633\u062a\u06af\u0627\u0647 \u0647\u0627\u06cc \u0645\u062a\u0635\u0644 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n<p>\u0645\u062b\u0627\u0644:<\/p>\n<div class=\"highlight js-code-highlight\">\n<pre class=\"highlight plaintext\"><code>matlab\n\n% Run arp command to list devices on the network\n[status, result] = system('arp -a');\n\n% Display the result\ndisp(result);\n<\/code><\/pre>\n<div class=\"highlight__panel js-actions-panel\">\n<div class=\"highlight__panel-action js-fullscreen-code-action\">\n    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-on\"><title>\u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u0631\u0627 \u0648\u0627\u0631\u062f \u06a9\u0646\u06cc\u062f<\/title>\n    <path d=\"M16 3h6v6h-2V5h-4V3zM2 3h6v2H4v4H2V3zm18 16v-4h2v6h-6v-2h4zM4 19h4v2H2v-6h2v4z\"\/>\n<\/svg><\/p>\n<p>    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-off\"><title>\u0627\u0632 \u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u062e\u0627\u0631\u062c \u0634\u0648\u06cc\u062f<\/title>\n    <path d=\"M18 7h4v2h-6V3h2v4zM8 9H2V7h4V3h2v6zm10 8v4h-2v-6h6v2h-4zM8 15v6H6v-4H2v-2h6z\"\/>\n<\/svg><\/p>\n<\/div>\n<\/div>\n<\/div>\n<p><strong>4. \u0627\u0632 \u0627\u0628\u0632\u0627\u0631\u0647\u0627\u06cc \u0641\u0631\u0648\u0634\u0646\u062f\u0647 FPGA \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f<\/strong><br \/>\u0628\u06cc\u0634\u062a\u0631 \u0641\u0631\u0648\u0634\u0646\u062f\u06af\u0627\u0646 FPGA \u0627\u0628\u0632\u0627\u0631\u06cc \u0628\u0631\u0627\u06cc \u062a\u0634\u062e\u06cc\u0635 \u0648 \u067e\u06cc\u06a9\u0631\u0628\u0646\u062f\u06cc \u062a\u0627\u0628\u0644\u0648\u0647\u0627\u06cc FPGA \u0627\u0631\u0627\u0626\u0647 \u0645\u06cc \u062f\u0647\u0646\u062f. \u0627\u06cc\u0646 \u0627\u0628\u0632\u0627\u0631\u0647\u0627 \u0627\u063a\u0644\u0628 \u0645\u06cc \u062a\u0648\u0627\u0646\u0646\u062f \u0622\u062f\u0631\u0633 IP \u0635\u0641\u062d\u0647 \u0645\u062a\u0635\u0644 \u0631\u0627 \u0646\u0634\u0627\u0646 \u062f\u0647\u0646\u062f.<\/p>\n<p><strong>A. Xilinx Live<\/strong><\/p>\n<ul>\n<li>Vivado \u0631\u0627 \u0628\u0627\u0632 \u06a9\u0646\u06cc\u062f \u0648 \u0628\u0647 \u0635\u0641\u062d\u0647 FPGA \u0648\u0635\u0644 \u0634\u0648\u06cc\u062f.<\/li>\n<li>\u0628\u0631\u0627\u06cc \u0645\u0634\u0627\u0647\u062f\u0647 \u0622\u062f\u0631\u0633 IP \u0647\u06cc\u0626\u062a \u0645\u062f\u06cc\u0631\u0647 \u0627\u0632 \u0645\u062f\u06cc\u0631 \u0633\u062e\u062a \u0627\u0641\u0632\u0627\u0631 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/li>\n<\/ul>\n<p><strong>B. \u06a9\u0648\u0627\u0631\u062a\u0648\u0633 \u0627\u06cc\u0646\u062a\u0644<\/strong><\/p>\n<ul>\n<li>\u06a9\u0648\u0627\u0631\u062a\u0648\u0633 \u0631\u0627 \u0628\u0627\u0632 \u06a9\u0631\u062f\u0647 \u0648 \u0628\u0647 \u0635\u0641\u062d\u0647 FPGA \u0645\u062a\u0635\u0644 \u0634\u0648\u06cc\u062f.<\/li>\n<li>\u0628\u0631\u0627\u06cc \u0645\u0634\u0627\u0647\u062f\u0647 \u0622\u062f\u0631\u0633 IP \u0647\u06cc\u0626\u062a \u0645\u062f\u06cc\u0631\u0647 \u0627\u0632 \u06a9\u0646\u0633\u0648\u0644 \u0633\u06cc\u0633\u062a\u0645 \u06cc\u0627 \u0627\u0634\u06a9\u0627\u0644 \u0632\u062f\u0627\u06cc\u06cc \u0632\u0646\u062c\u06cc\u0631\u0647 \u0627\u06cc JTAG \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/li>\n<\/ul>\n<p><strong>5. \u0627\u0632 \u062a\u0648\u0627\u0628\u0639 MATLAB TCP\/IP \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f<\/strong><br \/>\u0627\u06af\u0631 \u0635\u0641\u062d\u0647 FPGA \u0628\u0647 \u0639\u0646\u0648\u0627\u0646 \u0633\u0631\u0648\u0631 TCP\/IP \u067e\u06cc\u06a9\u0631\u0628\u0646\u062f\u06cc \u0634\u062f\u0647 \u0628\u0627\u0634\u062f \u060c \u0645\u06cc \u062a\u0648\u0627\u0646\u06cc\u062f \u0627\u0632 \u062a\u0648\u0627\u0628\u0639 TCP\/IP MATLAB \u0628\u0631\u0627\u06cc \u0627\u06cc\u062c\u0627\u062f \u0627\u062a\u0635\u0627\u0644 \u0648 \u0628\u0627\u0632\u06cc\u0627\u0628\u06cc \u0622\u062f\u0631\u0633 IP \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n<p>\u0645\u062b\u0627\u0644:<\/p>\n<div class=\"highlight js-code-highlight\">\n<pre class=\"highlight plaintext\"><code>matlab\n\n% Create a TCP\/IP object\ntcpipObj = tcpip('fpga_hostname', 7); % Replace 'fpga_hostname' with the board's hostname\n\n% Open the connection\nfopen(tcpipObj);\n\n% Get the remote IP address\nipAddress = tcpipObj.RemoteHost;\n\n% Display the IP address\ndisp(ipAddress);\n\n% Close the connection\nfclose(tcpipObj);\n<\/code><\/pre>\n<div class=\"highlight__panel js-actions-panel\">\n<div class=\"highlight__panel-action js-fullscreen-code-action\">\n    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-on\"><title>\u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u0631\u0627 \u0648\u0627\u0631\u062f \u06a9\u0646\u06cc\u062f<\/title>\n    <path d=\"M16 3h6v6h-2V5h-4V3zM2 3h6v2H4v4H2V3zm18 16v-4h2v6h-6v-2h4zM4 19h4v2H2v-6h2v4z\"\/>\n<\/svg><\/p>\n<p>    <svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" class=\"highlight-action crayons-icon highlight-action--fullscreen-off\"><title>\u0627\u0632 \u062d\u0627\u0644\u062a \u062a\u0645\u0627\u0645 \u0635\u0641\u062d\u0647 \u062e\u0627\u0631\u062c \u0634\u0648\u06cc\u062f<\/title>\n    <path d=\"M18 7h4v2h-6V3h2v4zM8 9H2V7h4V3h2v6zm10 8v4h-2v-6h6v2h-4zM8 15v6H6v-4H2v-2h6z\"\/>\n<\/svg><\/p>\n<\/div>\n<\/div>\n<\/div>\n<p><strong>6. \u0645\u0633\u062a\u0646\u062f\u0627\u062a \u0647\u06cc\u0626\u062a \u0645\u062f\u06cc\u0631\u0647 FPGA \u0631\u0627 \u0628\u0631\u0631\u0633\u06cc \u06a9\u0646\u06cc\u062f<\/strong><br \/>\u0628\u0631\u0627\u06cc \u062f\u0633\u062a\u0648\u0631\u0627\u0644\u0639\u0645\u0644 \u0647\u0627\u06cc \u062e\u0627\u0635 \u062f\u0631 \u0645\u0648\u0631\u062f \u06cc\u0627\u0641\u062a\u0646 \u0622\u062f\u0631\u0633 IP \u062e\u0648\u062f \u0628\u0647 \u06a9\u062a\u0627\u0628\u0686\u0647 \u0631\u0627\u0647\u0646\u0645\u0627\u06cc \u06a9\u0627\u0631\u0628\u0631 \u06cc\u0627 \u0645\u0633\u062a\u0646\u062f\u0627\u062a \u06a9\u0627\u0631\u0628\u0631 FPGA \u0645\u0631\u0627\u062c\u0639\u0647 \u06a9\u0646\u06cc\u062f. \u0628\u0631\u062e\u06cc \u0627\u0632 \u062a\u0627\u0628\u0644\u0648\u0647\u0627 \u062f\u0627\u0631\u0627\u06cc \u06cc\u06a9 \u0622\u062f\u0631\u0633 IP \u067e\u06cc\u0634 \u0641\u0631\u0636 \u0647\u0633\u062a\u0646\u062f \u06cc\u0627 \u0631\u0627\u0647\u06cc \u0628\u0631\u0627\u06cc \u067e\u06cc\u06a9\u0631\u0628\u0646\u062f\u06cc \u0622\u0646 \u0627\u0632 \u0637\u0631\u06cc\u0642 \u0631\u0627\u0628\u0637 \u0648\u0628 \u06cc\u0627 \u0627\u062a\u0635\u0627\u0644 \u0633\u0631\u06cc\u0627\u0644 \u0627\u0631\u0627\u0626\u0647 \u0645\u06cc \u062f\u0647\u0646\u062f.<\/p>\n<p><strong>7. \u0645\u062b\u0627\u0644: \u0635\u0641\u062d\u0647 Xilinx Zynq \u0628\u0627 Matlab<\/strong><br \/>\u0627\u06af\u0631 \u0627\u0632 \u0635\u0641\u062d\u0647 Xilinx Zynq \u0628\u0627 MATLAB \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0645\u06cc \u06a9\u0646\u06cc\u062f:<\/p>\n<ol>\n<li>\n<p>\u0635\u0641\u062d\u0647 \u0631\u0627 \u0627\u0632 \u0637\u0631\u06cc\u0642 \u0627\u062a\u0631\u0646\u062a \u0628\u0647 \u0631\u0627\u06cc\u0627\u0646\u0647 \u062e\u0648\u062f \u0648\u0635\u0644 \u06a9\u0646\u06cc\u062f.<\/p>\n<\/li>\n<li>\n<p>\u0628\u0631\u0627\u06cc \u062a\u0634\u062e\u06cc\u0635 \u0635\u0641\u062d\u0647 \u0648 \u0628\u0627\u0632\u06cc\u0627\u0628\u06cc \u0622\u062f\u0631\u0633 IP \u0622\u0646 \u060c \u0627\u0632 \u0639\u0645\u0644\u06a9\u0631\u062f Xilinx.fpga.board.listavailableboards \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n<\/li>\n<li>\n<p>\u0627\u0632 \u0637\u0631\u0641 \u062f\u06cc\u06af\u0631 \u060c \u0628\u0631\u0627\u06cc \u06cc\u0627\u0641\u062a\u0646 \u0622\u062f\u0631\u0633 IP \u0627\u0632 \u0645\u062f\u06cc\u0631 \u0633\u062e\u062a \u0627\u0641\u0632\u0627\u0631 Xilinx Vivado \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n<\/li>\n<\/ol>\n<p>\u0628\u0627 \u062f\u0646\u0628\u0627\u0644 \u06a9\u0631\u062f\u0646 \u0627\u06cc\u0646 \u0645\u0631\u0627\u062d\u0644 \u060c \u0645\u06cc \u062a\u0648\u0627\u0646\u06cc\u062f \u0622\u062f\u0631\u0633 IP \u06cc\u06a9 \u0635\u0641\u062d\u0647 FPGA \u0631\u0627 \u06a9\u0647 \u0627\u0632 \u0637\u0631\u06cc\u0642 MATLAB \u0645\u062a\u0635\u0644 \u0627\u0633\u062a \u060c \u067e\u06cc\u062f\u0627 \u06a9\u0646\u06cc\u062f \u0648 \u0628\u0631\u0627\u06cc \u062a\u0648\u0633\u0639\u0647 \u0648 \u0622\u0632\u0645\u0627\u06cc\u0634 \u0628\u06cc\u0634\u062a\u0631 \u0627\u0631\u062a\u0628\u0627\u0637 \u0628\u0631\u0642\u0631\u0627\u0631 \u06a9\u0646\u06cc\u062f.<\/p>\n<\/p><\/div>\n","protected":false},"excerpt":{"rendered":"<p>\u0628\u0631\u0627\u06cc \u06cc\u0627\u0641\u062a\u0646 \u0622\u062f\u0631\u0633 IP \u06cc\u06a9 \u0635\u0641\u062d\u0647 FPGA \u06a9\u0647 \u0627\u0632 \u0637\u0631\u06cc\u0642 MATLAB \u0645\u062a\u0635\u0644 \u0627\u0633\u062a \u060c \u0628\u0647 \u0637\u0648\u0631 \u0645\u0639\u0645\u0648\u0644 \u0628\u0627\u06cc\u062f \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u06cc\u06a9 \u0631\u0627\u0628\u0637 \u067e\u0634\u062a\u06cc\u0628\u0627\u0646\u06cc \u0634\u062f\u0647 (\u0628\u0647 \u0639\u0646\u0648\u0627\u0646 \u0645\u062b\u0627\u0644 \u060c \u0627\u062a\u0631\u0646\u062a \u060c JTAG \u06cc\u0627 PCIE) \u0627\u0631\u062a\u0628\u0627\u0637 \u0628\u06cc\u0646 MATLAB \u0648 \u0635\u0641\u062d\u0647 FPGA \u0628\u0631\u0642\u0631\u0627\u0631 \u06a9\u0646\u06cc\u062f. \u0645\u0631\u0627\u062d\u0644 \u062f\u0642\u06cc\u0642 \u0628\u0647 \u0635\u0641\u062d\u0647 FPGA \u060c \u067e\u0631\u0648\u062a\u06a9\u0644 \u0627\u0631\u062a\u0628\u0627\u0637\u06cc \u0648 \u0627\u0628\u0632\u0627\u0631\u06cc \u06a9\u0647 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0645\u06cc &hellip;<\/p>\n","protected":false},"author":2,"featured_media":102210,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"fifu_image_url":"https:\/\/media2.dev.to\/dynamic\/image\/width=1000,height=500,fit=cover,gravity=auto,format=auto\/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fd8mdwz7u9hzksfe45g3p.png","fifu_image_alt":"","footnotes":""},"categories":[339],"tags":[],"class_list":["post-102209","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-dev"],"_links":{"self":[{"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/posts\/102209","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/comments?post=102209"}],"version-history":[{"count":0,"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/posts\/102209\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/media\/102210"}],"wp:attachment":[{"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/media?parent=102209"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/categories?post=102209"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/nabfollower.com\/blog\/wp-json\/wp\/v2\/tags?post=102209"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}